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complete 14-bit ccd/cis signal processor ad9822 rev. b in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . features 14-bit 15 msps adc no missing codes guarantee d 3-channel operation up to 15 msps 1-channel operation up to 12. 5 msps correlated dou b le sampling 1C6 programmable gain 350 m v programmable offse t input clamp circuitry internal voltag e reference multiplexed byte-wide outp ut (8 + 6 format) 3-wire seri al di gital interface 3 v/5 v digita l i / o co mpatibility 28-lead soic or ssop low power cmos: 385 mw (t y p ) power-down mode: <1 m w applic ati o ns flatbed document scanners film scanners digital color copiers multifunction peripherals general description the ad9822 is a co m p lete a n al og sig n al p r o c es s o r f o r ccd i m a g in g a p p l ica t i o n s . i t fe a t ur es a 3- ch a n n e l a r c h i t ec t u r e d e si g n e d to s a m p l e a n d c o nd it i o n t h e output s of t r i l i n e a r c o l o r c c d a r ra y s . e a ch channe l con s ists o f an in p u t c l am p , co r r el a t e d doub l e sa m p le r (cd s ), o f fset d a c , a n d p r ogra mm a b le ga in a m pli f ie r (pga) m u l t i p lex e d t o a hig h p e r f o r mance 14 -b i t ad c. the cds a m plif iers ma y b e dis a b l e d fo r us e w i t h s e n s o r s s u ch as co n t ac t im a g e s e n s o r s (cis) a nd cmos ac t i ve p i xel s e ns o r s, w h ich do n o t r e q u ir e cds. the 14-b i t dig i t a l o u t p u t is m u l t i p lexed in t o a n 8-b i t o u t p u t w o r d t h a t is a c c e ss e d usin g tw o r e ad c y cles. th e in t e r n a l re g i ste r s are pro g r a m m e d t h rou g h a 3 - w i re s e r i a l i n te r f a c e a n d p r o v ide ad j u s t m e n t o f t h e ga in, o f fs et, a n d op era t in g m o de . the ad9822 o p era t es f r o m a sin g le 5 v p o w e r s u p p l y , co n s u m es 385 mw o f p o w e r typ i cal l y , a nd is p a c k a g e d in a 28-lead so i c or sso p . func tio n a l block di agram 14 8 band gap reference configuration register mux register 66 99 gain registers offset registers digital control interface input clamp bias ad9822 drvdd drvss avdd avss capt capb avdd avss cml oeb dout adcclk cdsclk2 cdsclk1 offset vinb ving vinr 9-bit dac 00623-001 sclk sload sdata 9-bit dac 9-bit dac cds pga pga pga cds cds 3:1 mux 14-bit adc 14:8 mux blue green red blue green red fi g u r e 1 .
ad9822 rev. b | page 2 of 20 table of contents specifications ..................................................................................... 3 analog specifications ................................................................... 3 digital specifications ................................................................... 4 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 thermal characteristics .............................................................. 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 te r m i no l o g y ...................................................................................... 8 functional description .................................................................. 12 3-channel cds mode ................................................................ 12 3-channel sha mode ................................................................ 12 1-channel cds mode ............................................................... 12 1-channel sha mode ............................................................... 12 internal register descriptions .................................................. 13 circuit operation ........................................................................... 15 analog inputscds mode ...................................................... 15 external input coupling capacitors ........................................ 15 analog inputssha mode ...................................................... 16 programmable gain amplifiers (pga) .................................. 16 applications ..................................................................................... 17 circuit and layout recommendations ................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 2/05rev. a to rev. b changes to format .............................................................universal changes to ordering guide .......................................................... 18 updated outline dimensions ....................................................... 18 12/99rev. 0 to rev. a
ad9822 r e v. b | pa ge 3 o f 2 0 specifications analog s p ecifica t ions t min to t max , a v dd = 5 v , dr v d d = 5 v , c d s mo d e , f ad cc l k = 15 mh z, f cd s c lk1 = f cds c lk2 = 5 mh z, pga ga in = 1, unles s o t h e r w is e n o t e d . table 1. p a r a m e t e r m i n t y p m a x u n i t maxi mum con v ersion r a te 3-channe l mode with cds 15 msps 1-channe l mode with cds 12.5 msps accuracy (e n t ire s i gnal pa th) adc resolution 14 bits integral nonlinearity (in l ) ?17.0/ +3.5 lsb inl @ 6 mhz ?10.5/+1.5 lsb differential non l inearity ( d nl) ?0.65/+0.75 lsb dnl @ 6 mhz ?1.0 ?0.6/+0.65 +1.1 lsb no m i ssing cod e s 14 bits no mis s i ng codes @ 6 mhz 14 bits offset error ?240 ?19 +200 mv gain error ?1.4 +3.5 +6.9 % fsr analog in puts input signal range 1 2 . 0 v p - p allow a ble re set t r ansient 1 1 . 0 v input limits 2 avss ? 0.3 avdd + 0.3 v input capacitance 10 pf input bias current 10 na amplifie r s pga gain at min imum 1 v/v pga gain at ma ximum 5.7 v/v pga gain resolution 2 6 4 s t e p s pga gain monotonicity guaranteed programmable offset at minimum ?350 mv programmable offset at maximum +350 mv programmable offset resolution 512 steps programmab l e offset monoton i city guaranteed noise and c r osstalk total output no ise @ pga mini mum 1.5 lsb rms total output no ise @ pga max i mum 6.0 lsb rms channe l-to-cha nnel cro sstal k @ 6 m h z <1 lsb power supply rejection avdd = 5 v 0. 25 v 0.063 0.9 % fsr differen t ial v r ef ( @ 25c ) capt to ca pb (2 v adc f u ll-scale range) 0.94 1.0 1.06 v tempe r atu r e range o p e r a t i n g 0 + 7 0 c s t o r a g e ? 6 5 + 1 5 0 c power suppli e s a v d d 4 . 7 5 5 . 0 5 . 2 5 v d r v d d 3 . 0 5 . 0 5 . 2 5 v operatin g cu rren t a v d d 7 3 m a d r v d d 4 m a power-down mode current 150 a
ad9822 rev. b | page 4 of 20 parameter min typ max unit power dissipation 3-channel mode 385 450 mw 3-channel mode @ 6 mhz 335 410 mw 1-channel mode 300 mw 1-channel mode @ 6 mhz 250 mw 1 linear input signal range is from 2 v to 4 v when the ccds reference level is clamped to 4 v by the ad9822s input clamp. 1v typ reset transient 4v set by input clamp (3v option also available) 2v p-p max input signal range 00623-002 2 the pga gain is approximately line ar-in-db and follows the equation: [ ] ? ? ? ? ? ? ? + = 63 63 7.41 7.5 g gain where g is the register value. see figure . 15 digital specifications t min to t max , avdd = 5 v, drvdd = 5 v, cds mode, f adcclk = 15 mhz, f cdsclk1 = f cdsclk2 = 5 mhz, c l = 10 pf, unless otherwise noted. table 2. parameter symbol min typ max unit logic inputs high level input voltage v ih 2.0 v low level input voltage v il 0.8 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs high level output voltage v oh 4.5 v low level output voltage v ol 0.1 v high level output current i oh 50 a low level output current i ol 50 a
ad9822 rev. b | page 5 of 20 timing specifications t min to t max , avdd = 5 v, drvdd = 5 v. table 3. parameter symbol min typ max unit clock parameters 3-channel pixel rate t pra 67 ns 1-channel pixel rate t prb 80 ns adcclk pulse width t adclk 30 ns cdsclk1 pulse width t c1 10 ns cdsclk2 pulse width t c2 10 ns cdsclk1 falling to cdsclk2 rising t c1c2 0 ns adcclk falling to cdsclk2 rising t adc2 0 ns cdsclk2 rising to adcclk rising t c2adr 0 ns cdsclk2 falling to adcclk falling t c2adf 30 40 ns cdsclk2 falling to cdsclk1 rising t c2c1 30 40 ns adcclk falling to cdsclk1 rising t adc1 0 ns aperture delay for cds clocks t ad 2 ns serial interface maximum sclk frequency f sclk 10 mhz sload to sclk setup time t ls 10 ns sclk to sload hold time t lh 10 ns sdata to sclk rising setup time t ds 10 ns sclk rising to sdata hold time t dh 10 ns sclk falling to sdata valid t rdv 10 ns data output output delay t od 8 ns three-state to data valid t dv 10 ns output enable high to three-state t hz 10 ns latency (pipeline delay) 3 (fixed) cycles
ad9822 r e v. b | pa ge 6 o f 2 0 absolute maximum ratings table 4. parameter with respect t o m i n m a x u n i t vin, cap t , capb avss ?0.3 avdd + 0.3 v digital inputs avss ?0.3 avdd + 0.3 v a v d d a v s s ? 0 . 5 + 6 . 5 v d r v d d d r v s s ? 0 . 5 + 6 . 5 v a v s s d r v s s ? 0 . 3 + 0 . 3 v digital outputs drvss ?0.3 drvdd + 0.3 v junction tempe r ature 150 c storage temperature ?65 +150 c lead temperature (10 sec) 3 0 0 c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s r a t i ng o n ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or ot he r co ndi t i on s ab o v e t h o s e i ndic a te d in t h e op er a t i o na l s e c t io n s o f t h is sp e c if ic a t ion is n o t i m plie d . e x p o sur e t o a b s o l u t e maxi m u m ra tin g s f o r ext e n d e d p e r i o d s ma y a f f e ct d e vice r e liab ili t y . thermal c h aracteristics 28-l e ad 300 mi l so i c ja = 71.4c/w jc = 23c/w 28-l e ad 5.3 m m sso p ja = 109c/w jc = 39c/w esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad9822 r e v. b | pa ge 7 o f 2 0 pin conf iguration and fu nction descriptions 00623-003 cdsclk1 cdsclk2 adcclk oeb avdd 28 avss 27 vinr 26 offset 25 drvdd drvss (msb) d7 ving 24 cml 23 vinb 22 d6 capt 21 d5 capb 20 d4 10 avss 19 d3 11 avdd 18 d2 12 sload 17 d1 13 sclk 16 (lsb) d0 14 sdata 15 1 2 3 4 5 6 7 8 9 ad9822 top view (not to scale) f i gure 2. pin config ur ation ta ble 5. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic type 1 description 1 cdsclk1 di cds reference level samp ling c l ock. 2 cdsclk2 di cds data level sampling clock. 3 a d c c l k d i adc s a m p l i n g c l o c k . 4 oeb di output enable, active low. 5 drvdd p digital output driver supply. 6 drvss p digital output driver ground. 7 d7 (msb) do data output ms b. ad c db13 hi gh byte, adc d b 5 low byte. 8 d6 do data output. a d c db12 high byte, adc db4 low byte. 9 d5 do data output. a d c db11 high byte, adc db3 low byte. 10 d4 do data output. a d c db10 high byte, adc db2 low byte. 11 d3 do data output. a d c db9 high by te, adc db1 lo w byte. 12 d2 do data output. a d c db8 high by te, adc db0 lo w byte. 13 d1 do data output. a d c db7 hi gh by te, dont care low byte. 14 d0 (lsb) do data output ls b. adc db6 hig h byte, dont care low byte. 1 5 s d a t a d i / d o serial inte rface data input/ output. 16 sclk di serial interface clock input. 17 sload di serial interface load pulse. 18 avdd p 5 v analog supply. 1 9 a v s s p a n a l o g g r o u n d . 20 capb ao adc bottom ref e rence voltage decoupling. 21 capt ao adc top refere nce voltage decoupling. 22 vinb ai analog input, blue channel. 2 3 c m l a o internal bi a s lev e l decoupli ng. 24 ving ai analog input, green channel. 25 offset ao clamp bi as leve l decoupli ng. 26 vinr ai analog input, red channel. 2 7 a v s s p a n a l o g g r o u n d . 28 avdd p 5 v analog supply. 1 type: ai = an a l og i n put , ao = an a l og out p ut , d i = d i g i t a l in put , d o = d i g i t a l out p ut , p = pow e r.
ad9822 rev. b | page 8 of 20 terminology integral nonlinearity (inl) integral nonlinearity error refers to the deviation of each individual code from a line drawn from zero scale through positive full scale. the point used as zero scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1 ? lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinearity (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value; therefore, every code must have a finite width. no missing codes guaranteed to 14-bit resolution indicates that all 16384 codes, respectively, must be present over all operating ranges. offset error the first adc code transition should occur at a level ? lsb above the nominal zero-scale voltage. the offset error is the deviation of the actual first code transition level from the ideal level. gain error the last code transition should occur for an analog value 1 ? lsb below the nominal full-scale voltage. gain error is the deviation of the actual difference between the first and last code transitions and the ideal difference between the first and last code transitions. input referred noise the rms output noise is measured using histogram techniques. the adc output codes standard deviation is calculated in lsb and converted to an equivalent voltage, using the relationship 1 lsb = 4 v/16384 = 244 mv. the noise is then referred to the input of the ad9822 by dividing by the pga gain. channel-to-channel crosstalk in an ideal 3-channel system, the signal in one channel will not influence the signal level of another channel. the channel-to- channel crosstalk specification is a measure of the change that occurs in one channel as the other two channels are varied. in the ad9822, one channel is grounded and the other two channels are exercised with full-scale input signals. the change in the output codes from the first channel is measured and compared with the result when all three channels are grounded. the difference is the channel-to-channel crosstalk, stated in lsb. aperture delay the time delay that occurs from when a sampling edge is applied to the ad9822 until the actual sample of the input signal is held. both cdsclk1 and cdsclk2 sample the input signal during the transition from high to low; therefore, the aperture delay is measured from each clocks falling edge to the instant the actual internal sample is taken. power supply rejection it specifies the maximum full-scale change that occurs from the initial value when the supplies are varied over the specified limits.
ad9822 r e v. b | pa ge 9 o f 2 0 pixel n (r, g, b) pixel (n + 1) t ad t c2 t c2adf t adc2 t c2adr t adclk t adclk t od analog inputs cdsclk2 adcclk output data d<7:0> r (n ? 2) g (n ? 2) g (n ? 2) b (n ? 2) b (n ? 2) r (n ? 1) r (n ? 1) g (n ? 1) g (n ? 1) b (n ? 1) b (n ? 1) r (n) r (n) g (n) g (n) high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte t adc1 t ad t c1 cdsclk1 pixel (n + 2) 00623-004 t c2c1 t c1c2 t pra f i g u re 3. 3- chann e l cds m o de tim i ng t ad pixel n t ad analog inputs t od cdsclk2 adcclk output data d<7:0> t c2 pixel (n ? 4) pixel (n ? 4) pixel (n ? 3) pixel (n ? 3) pixel (n ? 2) pixel (n ? 2) t c1c2 t c1 cdsclk1 t adc1 high byte low byte low byte high byte low byte high byte pixel (n + 1) pixel (n + 2) t c2adr 00623-005 t c2c1 t prb t c2adf t adclk t adclk f i g u re 4. 1- chann e l cds m o de tim i ng
ad9822 rev. b | page 10 of 20 pixel n (r, g, b) pixel (n + 1) t ad t c2 t c2adf t adc2 t c2adr t adclk t adclk t od analog inputs cdsclk2 adcclk output data d<7:0> r (n ? 2) g (n ? 2) g (n ? 2) b (n ? 2) b (n ? 2) r (n ? 1) r (n ? 1) g (n ? 1) g (n ? 1) b (n ? 1) b (n ? 1) r (n) r (n) g (n) g (n) high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte 00623-006 t pra f i g u re 5. 3- chann e l s h a m o de tim i ng t od analog inputs cdsclk2 adcclk output data d<7:0> pixel n t ad high byte low byte low byte high byte high byte low byte pixel (n ? 4) pixel (n ? 4) pixel (n ? 3) pixel (n ? 3) pixel (n ? 2) pixel (n ? 2) t c2adr 00623-007 t c2 t prb t c2adf t adclk t adclk f i g u re 6. 1- chann e l s h a m o de tim i ng
ad9822 rev. b | page 11 of 20 t hz t dv t od t od a dccl k output data oeb high byte db13?db6 low byte db5? db0 high byte n + 1 low byte n + 1 low byte n + 2 high byte n + 3 pixel n pixel n 00623-008 f i gure 7 . d i gi tal o u tput da ta ti mi ng sdata sclk sload r/wb a2 a1 a0 xx xx d8 d7 d6 d5 d4 d3 d2 d1 d0 t ds t dh t ls t lh xx 00623-009 f i gure 8. s e r i a l w r ite o p er ati o n t i mi n g sdata sclk sload r/wb a2 a1 a0 xx xx xx d8 d7 d6 d5 d4 d3 d2 d1 d0 t ds t rdv t dh t ls t lh 00623-010 f i gur e 9 . s e ri al read op e r a t i o n tim i ng
ad9822 rev. b | page 12 of 20 functional description the ad9822 can be operated in four different modes: 3-channel cds mode, 3-channel sha mode , 1-channel cds mode, and 1-channel sha mode. each mode is selected by programming the configuration register through the serial interface. for more information on cds or sha mode operation, see the circuit operation section. 3-channel cds mode in 3-channel cds mode, the ad9822 simultaneously samples the red, green, and blue input voltages from the ccd outputs. the sampling points for each cds are controlled by cdsclk1 and cdsclk2 (see figure 10 and figure 11). cdsclk1s falling edge samples the reference level of the ccd waveform, and cdsclk2s falling edge samples the data level of the ccd waveform. each cds amplifier outputs the difference between the ccds reference and data levels. the output voltage of each cds amplifier is then level-shifted by an offset dac. the voltages are scaled by the three pgas before being multiplexed through the 14-bit adc. the adc sequentially samples the pga outputs on the falling edges of adcclk. the offset and gain values for the red, green, and blue channels are programmed using the serial interface. the order in which the channels are switched through the multiplexer is selected by programming the mux register. timing for this mode is shown in figure 3. it is recommended that the falling edge of cdsclk2 occur coincident with or before the rising edge of adcclk. however, this is not required to satisfy the minimum timing constraints. the rising edge of cdsclk2 should not occur before the previous falling edge of adcclk, as shown by t adc2 . the output data latency is three clock cycles. 3-channel sha mode in 3-channel sha mode, the ad9822 simultaneously samples the red, green, and blue input voltages. the sampling point is controlled by cdsclk2. cdsclk2s falling edge samples the input waveforms on each channel. the output voltages from the three shas are modified by the offset dacs and then scaled by the three pgas. the outputs of the pgas are then multiplexed through the 14-bit adc. the adc sequentially samples the pga outputs on the falling edges of adcclk. the input signal is sampled with respect to the voltage applied to the offset pin (see figure 12). with the offset pin grounded, a 0 v input corresponds to the adcs zero-scale output. the offset pin may also be used as a coarse offset adjust pin. a voltage applied to this pin is subtracted from the voltages applied to the red, green, and blue inputs in the first amplifier stage of the ad9822. the input clamp is disabled in this mode. for more information, see the circuit operation section. timing for this mode is shown in figure 5. cdsclk1 should be grounded in this mode. although not required, it is recommended that the falling edge of cdsclk2 occur coincident with or before the rising edge of adcclk. the rising edge of cdsclk2 should not occur before the previous falling edge of adcclk, as shown by t adc2 . the output data latency is three adcclk cycles. the offset and gain values for the red, green, and blue channels are programmed using the serial interface. the order in which the channels are switched through the multiplexer is selected by programming the mux register. 1-channel cds mode this mode operates in the same way as the 3-channel cds mode. the difference is that the multiplexer remains fixed in this mode; therefore, only the channel specified in the mux register is processed. timing for this mode is shown in figure 4. 1-channel sha mode this mode operates in the same way as the 3-channel sha mode, except the multiplexer remains stationary. only the channel specified in the mux register is processed. the input signal is sampled with respect to the voltage applied to the offset pin. with the offset pin grounded, a 0 v input corresponds to the adcs zero-scale output. the offset pin may also be used as a coarse offset adjust pin. a voltage applied to this pin is subtracted from the voltages applied to the red, green, and blue inputs in the first amplifier stage of the ad9822. the input clamp is disabled in this mode. for more information, see the circuit operation section. timing for this mode is shown in figure 6. cdsclk1 should be grounded in this mode of operation.
ad9822 rev. b | page 13 of 20 internal register descriptions table 6. internal register map register name address data bits a2 a1 a0 d8 d7 d6 d d4 d3 d2 d1 d0 configuration 0 0 0 0 0 vref 3ch/1ch cds on clamp pwr dn 0 0 mux 0 0 1 0 rgb/bgr red green blue 0 0 0 0 red pga 0 1 0 0 0 0 msb lsb green pga 0 1 1 0 0 0 msb lsb blue pga 1 0 0 0 0 0 msb lsb red offset 1 0 1 msb lsb green offset 1 1 0 msb lsb blue offset 1 1 1 msb lsb configuration register the configuration register controls the ad9822s operating mode and bias levels. bits d8, d1, and d0 should always be set low. bit d7 sets the full-scale voltage range of the ad9822s adc to either 4 v (high) or 2 v (low). bit d6 controls the internal voltage r eference. if the ad9822s internal voltage reference is used, this bit is set high. setting bit d6 low disables the internal voltage reference, allowing an external voltage reference to be used. bit d5 configures the ad9822 for either the 3-channel (high) or 1-channel (low) mode of operation. setting bit d4 high enables the cds mode of operation and setting this bit low enables the sha mode of operation. bit d3 sets t he dc bias level of the ad9822s input clamp. this bit should always be set high for the 4 v clamp bias, unless a ccd with a reset feedthr ough transient exceeding 2 v is used. if the 3 v clamp bias level is used, the peak-to-peak input signal range to the ad9822 is redu ced to 3 v maximum. bit d2 controls the power-down mode. setting bit d2 high places the ad9822 into a very low power sleep mode. all reg ister contents are retained while the ad 9822 is in the power-down state. table 7. configuration register settings d8 d7 d6 d5 d4 d3 d2 d1 d0 set to 0 set to 0 internal vref no. of channels cds operation input clamp bias power-down set to 0 set to 0 1 = enabled 1 1 = 3-ch mode 1 1 = cds mode 1 1 = 4 v 1 1 = on 0 = disabled 0 = 1-ch mode 0 = sha mode 0 = 3 v 0 = off (normal) 1 1 power-on default value. mux register the mux register controls the sampling channel order in the ad9822. bits d8, d3, d2, d1, and d0 should always be set low. bit d7 is used when operating in 3-channel mode. setting bit d7 high sequences the mux to sample the red channel first, then the green ch annel, and then the blue channel. when in this mode, the cdsclk2 pulse always resets the mux to sample the red channel first (see figu re 3). when bit d7 is set low, the channel order is reversed to blue first, green second, and red third. the cdsclk2 pulse always rese ts the mux to sample the blue channel first. bits d6, d5, and d4 are used when operating in 1-channel mode. bit d6 is set high to samp le the red channel. bit d5 is set high to sample the green channel. bit d4 is set high to sample the blue channel. the mux remains sta tionary during 1-channel mode. table 8. mux register settings d8 d7 d6 d5 d4 d3 d2 d1 d0 set to 0 3-channel select 1-channel select 1-channel select 1-channel select set to 0 set to 0 set to 0 set to 0 1 = r-g-b 1 1 = red 1 1 = green 1 = blue 0 = b-g-r 0 = off 0 = off 1 0 = off 1 1 power-on default value.
ad9822 rev. b | page 14 of 20 pga gain registers there are three pga registers for individually programming the gain in the red, green, and blue channels. bits d8, d7, and d6 i n each register must be set low, and bits d5 through d0 control the gain range in 64 increments. see figure 15 for the pga gain vs. th e pga register code. the coding for the pga registers is straight binary , with an all 0s word corresponding to the minimum gain setti ng (1) and an all 1s word corresponding to the maximum gain setting (5.7). table 9. pga gain register settings d8 d7 d6 d5 d4 d3 d2 d1 d0 set to 0 set to 0 set to 0 msb lsb gain (v/v) gain (db) 0 0 0 0 0 0 0 0 0 1 1.0 0.0 0 0 0 0 0 0 0 0 1 1.013 0.12 ? ? ? ? ? ? ? ? ? 0 0 0 1 1 1 1 1 0 5.4 14.6 0 0 0 1 1 1 1 1 1 5.7 15.1 1 power-on default value. offset registers there are three pga registers for individually programming the offset in the red, green, and blue channels. bits d8 through d0 control the offset range from ?350 mv to +350 mv in 512 increments. the codi ng for the offset registers is sign magnitude, with d8 as t he sign bit. table 10 shows the offset range as a function of the bits d8 through d0. table 10. offset register settings d8 (msb) d7 d6 d5 d4 d3 d2 d1 d0 (lsb) offset (mv) 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 +1.2 ? ? ? ? ? ? 0 1 1 1 1 1 1 1 1 +350 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ?1.2 ? ? ? ? ? ? 1 1 1 1 1 1 1 1 1 ?350 1 power-on default value.
ad9822 rev. b | page 15 of 20 circuit ope ration analog inputsc ds mode f i gur e 10 sh o w s t h e a n a l og in p u t co nf igura t ion fo r t h e cds mo d e of op e r a t i o n . f i g u re 1 1 sh ow s t h e i n te r n a l t i m i ng f o r t h e s a m p ling s w i t ches. th e c c d r e fer e n c e l e v e l is s a m p le d w h e n c d s c l k 1 t r an s i t i ons f r om h i g h to l o w , op e n i n g s 1 . t h e c c d da ta lev e l i s s a m p led w h en c d sc l k 2 tra n si ti o n s f r o m h i gh t o lo w , o p enin g s2. s3 is t h en clos e d , g e nera t i n g a dif f er en t i al o u t p ut v o l t a g e r e p r es en t i n g t h e dif f er en ce b e twe e n t h e tw o s a m p le d le v e l s. the in p u t cla m p is co n t r o l l ed b y cdsclk1. w h en cds c lk1 is hig h , s4 clo s es and t h e in ter n a l b i as vol t a g e is c o nn e c te d to t h e a n alog in p u t. th e b i as v o l t a g e cha r g e s t h e ext e r n al 0.1 f in p u t ca p a c i t o r , lev e l -s hif t ing the ccd sig n al in t o the ad9822 s in p u t co mm o n -mo d e ra n g e . th e time co n s tan t o f t h e in p u t c l am p is de te r m i n e d b y t h e i n te r n a l 5 k ? re s i st anc e and t h e e x te r n a l 0.1 f in p u t ca p a ci tan c e . ad9822 s1 s2 2pf s3 2pf cml cml avdd 4v s4 5k ? 1.7k ? vinr offset c in 0.1 f ccd signa l 0.1 f 1 f + 3v 2.2k ? 6.9k ? input clamp level is selected in the configuration register. 00362-011 f i g u re 10. cds m o de input conf ig u r a t ion (a ll t h ree c h a nnels are id ent i c a l) cdsclk1 cdsclk2 q3 (internal) s1, s4 closed s1, s4 closed s2 closed s2 closed s3 closed s3 closed s3 open s2 open s1, s4 open 00623-012 f i gure 11. cds m o de intern al switch t i ming external input cou p ling capac i tors the r e co m m e nde d va l u e fo r t h e in p u t co u p li ng ca p a c i to rs is 0.1 f . w h ile i t is p o s s i b le t o us e a smal ler ca p a c i t o r , this la rg er val u e is c h osen f o r sev e ral r e as o n s: ? si g n a l a tte n u a t i o n: t h e i n put c o upl i ng c a p a c i t o r c r e a te s a ca p a c i ti v e divider wi t h a cm o s in teg r a t e d cir c ui t s in p u t ca pa ci ta n c e , a t t e n u a t i n g t h e ccd s i gn al l e v e l . ci n s h o u l d be la r g e r e la ti v e t o th e i c s 10 pf i n p u t ca pa ci ta n c e i n o r d e r t o mini mi ze t h is e f fe c t . ? li n e a r i t y : s o m e o f th e i n p u t ca pa ci ta n c e o f a cm o s i c i s j u nc t i o n c a p a c i t a nc e, w h i c h v a r i e s non l i n e a r l y w i t h a p pl i e d vol t age. i f t h e i n put c o upl i ng c a p a c i tor i s to o s m a l l, t h e a t t e n u a t io n o f t h e c c d sig n al va r i es n o nli n e a rl y wi t h sig n al l e vel. thi s de g r a d e s t h e s y ste m l i ne ar i t y p e r f or manc e. ? s a mp l i n g e r r o r s : t h e i n t e r n a l 2 p f s a mp l e c a p a c i t o r s h a v e a m e m o r y o f t h e p r e v io us l y s a m p le d pixe l . ther e is a cha r g e r e dist r i b u t i o n e r r o r b e tw e e n ci n an d t h e in ter n a l s a m p le ca p a c i t o rs fo r la rg er p i xe l-t o -p i x e l v o l t a g e s w i n gs. a s t h e val u e o f cin is r e d u ce d , t h e r e su l t in g er r o r in t h e s a m p le d v o l t a g e in cr eas e s. w i th a ci n val u e o f 0.1 f , th e c h a r g e r e dis t r i b u tio n e r r o r is les s tha n 1 ls b f o r a f u l l -s cale , p i xe l-t o - pi x e l vo lt ag e s w i n g .
ad9822 rev. b | page 16 of 20 analog inputss ha mode f i gur e 12 sh o w s t h e a n a l og in p u t co nf igura t ion fo r t h e s h a mo d e of op e r a t i o n . f i g u re 1 3 sh ow s t h e i n te r n a l t i m i ng f o r t h e sa m p l i n g sw i t c h e s . t h e i n p u t s i g n al i s sa m p l e d wh e n cd s c lk2 t r ans i t i ons f r om h i g h to l o w , op e n i n g s 1 . t h e v o lt age o n t h e o ffs et p i n is als o s a m p led on th e fal l in g edg e o f cdsclk2, w h en s2 op en s. s3 is t h e n clos e d , g e nera t i n g a dif f er en t i al o u t p ut v o l t a g e r e p r es en t i n g t h e dif f er en ce b e twe e n t h e s a m p le d i n put vol t ag e and t h e of f s e t vol t age. t h e i n put cl am p i s d i sa b l e d d u r i n g s h a m o de o p er a t i o n. ad9822 s1 2pf s3 cml vinr input signal s2 2pf cml offset red ving green vinb blue optional dc offset (or connect to gnd) 00623-013 f i g u re 12. sha m o de input conf ig u r a t ion (a ll t h ree c h a nnels are id ent i c a l) cdsclk2 q3 (internal) s1, s2 closed s1, s2 closed s3 closed s3 closed s3 open s1, s2 open 00623-014 f i gure 13. sha m o de intern al switch t i ming f i gur e 14 s h o w s h o w the o ffs et p i n ma y b e us ed in a cis ap p l i c at i o n f o r c o a r s e o f f s e t a d j u s t m e nt . m a n y c i s s i g n a l s h a v e dc o f fs ets r a n g in g f r o m s e ver a l h u ndr e d mi l l i v ol ts to m o r e t h an 1 v . by co nn e c t i n g t h e a p p r o p r i a t e dc v o l t a g e t o t h e o ffs et p i n, t h e cis sig n al is r e s t o r e d to 0. af t e r t h e la rg e dc o f fs et is r e m o v e d , t h e sign al ca n b e scaled usi n g t h e pga t o m a xi mi ze t h e a d c s dy n a m i c r a nge. ad9822 offset red-offset green-offset blue-offset vinr ving vinb red green blue 0.1 f avdd vref from cis module dc offset r1 r2 sha 00623-015 sha sha f i gure 14. sha m o de used w i th e x te r n al dc o ffset programm able gain amplifiers (pga ) the ad9822 us es o n e p g a f o r eac h c h a n ne l . e a c h pga has a ga in ra n g e f r o m 1 (0 db) t o 5.8 (15.5 db), ad j u s t ab le in 64 s t eps. f i gur e 15 s h o w s t h e p g a ga in as a f u n c tion o f th e pga r e g i s t er co de . a l t h o u g h t h e ga in c u r v e is a p p r o x ima t e l y lin e ar -i n- db , t h e ga in i n v/ v var i es n o n l i n e a rly wi t h r e g i ster cod e , f o llo w i n g th e e q ua ti o n ? ? ? ? ? ? ? + = 63 63 4.7 1 5.7 g gain w h er e g is t h e de cimal val u e o f t h e ga i n r e g i st er co n t e n ts and va r i es f r o m 0 t o 63. 00623- 016 gain (v/v) 1.0 5.7 4.0 5.0 2.0 3.0 pga register value (decimal) 63 0 4 8 1 21 62 0 2 42 8 3 23 64 0 4 44 85 2 5 66 0 gain (db) 15 12 9 6 3 0 f i g u re 15. pg a g a i n t r ans f er f u nc t i o n
ad9822 rev. b | page 17 of 20 appli c ations circuit and layout r e commendations f i gur e 16 sh o w s t h e r e co m m e nde d cir c ui t co nf igur a t io n fo r 3- c h a n n e l cds m o de o p er a t i o n. t h e r e co mm en d e d in p u t co u p lin g c a p a ci t o r val u e is 0.1 f (s e e t h e cir c ui t o p era t io n s e c t i o n ) . a s i ng l e g r ou nd p l a n e i s re c o m m e nd e d for t h e ad9822. a s e p a ra t e p o w e r s u p p l y ma y be us e d f o r d r vd d , t h e d i g i t a l dr ive r su p p ly , b u t t h i s su p p ly p i n s h ou l d st i l l b e deco u p led t o the s a m e g r o u nd p l an e as t h e r e st o f th e ad9822. t h e l o a d i n g of t h e d i g i t a l output s s h ou l d b e m i n i m i z e d, e i t h e r b y usin g s h o r t t r aces t o th e dig i tal as i c o r b y usin g ext e r n al dig i t a l b u f f ers. t o minimize t h e ef fe c t o f dig i t a l t r a n sien ts d u ri n g m a jo r o u t p u t cod e tra n si ti o n s, th e fallin g ed g e o f c d s c lk 2 s h o u l d oc cu r c o i n ci de n t w i th o r be f o r e th e ri s i n g e d ge of a d c c l k ( s e e f i g u re 3 t h rou g h f i g u re 6 f o r t i m i ng ) . al l 0.1 f deco u p lin g c a p a ci t o rs s h o u ld b e lo ca t e d as c l os e as p o s s i b le t o t h e ad9822 p i n s . w h en o p era t ing in sin g le-c ha nn el m o de , the un us ed a n alog in p u ts s h o u ld b e g r o u n d e d . f i gur e 17 sh o w s t h e r e co m m e nde d cir c ui t co nf igur a t io n fo r 3 - ch an nel sh a mo d e . a l l of t h e ab ove c o ns i d e r a t i o ns a l s o a p pl y fo r t h is co nf igura t io n, excep t t h a t t h e a n a l og i n p u t sig n a l s a r e dir e c t ly co nne c t e d to t h e ad98 22 wi t h o u t t h e us e o f co u p lin g ca pa ci t o r s . th e a n alog i n p u t si g n als m u s t alr e ad y be d c - b ia se d b e tw e e n 0 v and 2 v (s e e t h e c i r c ui t o p er a t ion s e c t ion). 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad9822 cdsclk1 avdd cdsclk2 adcclk oeb drvdd drvss d7 (msb) d6 d5 d4 d3 d2 d1 d0 (lsb) avss vinr offset ving cml vinb capt capb avss avdd sload sclk sdata 3 clock inputs 8 data output s 0.1 f 3 serial interface 0.1 f 5v/3v 5v 0.1 f 0.1 f 0.1 f 0.1 f red input green input blue input 0.1 f 0.1 f 1.0 f 0.1 f 0.1 f + 10 f 5v 0.1 f 00623-017 f i gure 16. r e c o m m e nded c i rcuit co nf igur a t io n, 3 - cha nne l cds mo de 00623-018 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad9822 cdsclk1 avdd cdsclk2 adcclk oeb drvdd drvss d7 (msb) d6 d5 d4 d3 d2 d1 d0 (lsb) avss vinr offset ving cml vinb capt capb avss avdd sload sclk sdata 3 clock inputs 8 data output s 0.1 f 3 serial interface 0.1 f 5v/3v 5v 0.1 f red input green input blue input 0.1 f 0.1 f 0.1 f + 10 f 5v 0.1 f f i gure 17. rec o mmended c i rcuit conf igur ation, 3- chan n e l s h a mo d e ( a na lo g inputs s a m p l e d wi th resp ect t o gro u nd)
ad9822 rev. b | page 18 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ae 0.33 (0.0130) 0.20 (0.0079) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 28 15 14 1 18.10 (0.7126) 17.70 (0.6969) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) coplanarity 0.10 f i gure 18. 28-l ead standar d s m all o u tline p a ck age [s oi c ] w i de body (r - 2 8) di me nsio ns sho w n i n mi ll im e t e r s a n d (i nc he s) 0.25 0.09 0.95 0.75 0.55 8 4 0 0.05 min 1.85 1.75 1.65 2.00 max 0.38 0.22 seating plane 0.65 bsc coplanarity 0.10 28 15 14 1 10.50 10.20 9.90 5.60 5.30 5.00 8.20 7.80 7.40 pin 1 compliant to jedec standards mo-150ah f i gure 19. 2 8 -l ead shrink sm al l o u t lin e p a ckage [s sop ] (r s-28) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package options ad9822jr 0c to 70c 28-lead soic r-28 ad9822jrrl 0c to 70c 28-lead soic r-28 ad9822jrs 0c to 70c 28-lead ssop rs-28 AD9822JRSRL 0c to 70c 28-lead ssop rs-28 ad9822jrsz 1 0c to 70c 28-lead ssop rs-28 ad9822jrszrl 1 0c to 70c 28-lead ssop rs-28 1 z = pb-free part.
ad9822 rev. b | page 19 of 20 notes
ad9822 rev. b | page 20 of 20 notes ? 2005 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c00623C0 C 2/05(b)

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